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IP113F
Preliminary Data Sheet
Managed 10/100Base-TX / FX Media Converter
Features
A 10/100BASE-TX/ 100BASE-FX converter with a SMI port for management Built in a 10/100BASE-TX transceiver Built in a PHY for 100BASE-FX Built in a 2-port switch - Pass all packets without address and CRC check (optional) - Supports modified cut-through frame forwarding for low latency - Supports pure converter mode data forwarding for extreme low latency - Supports flow control for full and half duplex operation - Bandwidth control - Forward 1600 bytes packet for management - Optional forward fragments Built in 128Kb RAM for data buffer Supports 3.3v I/O tolerance SMI (MDC, MDIO) and MII registers for management - Configure local and remote IP113F through local SMI - Monitor local and remote IP113F through local SMI - Configure/ monitor TP port support (auto-negotiation or force 10M/100M, full/half) - Configure/ monitor flow control, bandwidth - Supports loop back test (In-band or out-band, auto or program) - The maintenance frame is compatible to TS-1000 standard (the Telecommunication Technology Committee, TTC) Supports Statistic Counters Supports auto MDI-MDIX function Supports link fault pass through function Supports far end fault function LED display for link/activity, full/half, 10/100 Built in a watchdog timer to monitor internal switch error Supports EEPROM Configuration 0.25u CMOS technology Single 2.5V power supply 48-pin LQFP package
General Description
IP113F can be a 10/100BASE-TX to 100BASE-FX converter or a 100BASE-FX to 100BASE-FX repeater with an SMI port for management. It consists of a 2-port switch controller, a fast Ethernet transceiver and a PHY for 100BASE-FX. The transceivers in IP113F are designed in DSP approach with advance 0.25um technology; this results in high noise immunity and robust performance. IP113F not only supports store and forward mode, it also supports modified cut through mode and pure converter mode for low latency data forwarding. IP113F can transmit packet(s) up to 1600 bytes to meet requirement of extra long packets. IP113F supports remote management function. IP113F supports remote access functions and it also supports remote monitor and loop back test function defined in TS-1000 spec. Local IP113F can access the MII register of remote IP113F by programming local IP113F's MII registers via SMI connection. IP113F implements the management function using the maintenance frame defined in TS-1000 spec. IP113F supports IEEE802.3x, collision base backpressure, and various LED functions, etc. These functions can be configured to fit the different requirements by feeding operation parameters via EEPROM interface or pull up/down resistors on specified pins.
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Aug. 20, 2003 IP113F-DS-R02
IP113F
Preliminary Data Sheet
Block Diagram
MDC MDIO
MII registers
SSRAM
PLL/ Clock Generator
RXIP RXIM TXOP TXOM
10/100M TX PHY
MII
Two port switch
MII
100M FX
FXSD FXRDP FXRDM FXTDP FXTDM
SCL SDA
EEPROM I/F
Forward Mode Control
LED I/F
LED
Remote Control
Application Diagram
FX
Fiber Module
IP113F
TX
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IP113F
Preliminary Data Sheet
Applications
Managed converter (up to 31 pieces of IP113F in a chassis)
VCC
FAST_FWD
MDC, MDIO IP113F
uC (for management) X1
X 31
Un-managed converter
VCC DIRECT_WIRE TP_FORCE SPEED_MODE DUPLEX_MODE IP113F
100BASE-TX
PHY1
SWITCH (un-used)
100BASE-FX
PHY2
RAM (un-used)
Fiber Repeater
VCC
100BASE-FX
PHY1
SWITCH
TWO_FIBER
100BASE-FX
PHY2
RAM
IP113F
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IP113F
Preliminary Data Sheet
PIN Diagram
LED_FX_SD/ SPEED_MODE 38
SCL / ADDR0
MDIO
OSCI
MDC
GND
GND
VCC
48
47
46
45
44
43
42
41
40
39
VCC
SDA
X2
37 36 35 34 33 32
LED_FX_FDX/ ADDR2
AVCC BGRES AUTO_TEST GND RXIP RXIM AVCC TXOP TXOM GND AVCC ADDR1
1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 12
LED_FX_LINK/ FX_FULL GND_IO VCC_IO LED_TP_SPD/ TWO_FIBER LED_TP_FDX/ ADDR3 LED_TP_LINK/ ADDR4 LED_FX_FEF_DET/ DUPLEX_MODE LED_RMT_TP_LINK/ X_EN RESETB TSE TSM LED_RMT_TP_SPD/ AUTO_SEND
IP113F
31 30 29 28 27 26 25
INTB
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LED_RMT_TP_FDX/ TP_FORCE
FXRDP
DIRECT_WIRE
FAST_FWD
FXRDM
FXTDM
FXSD
FXTDP
VCC
GND
LFP
Aug. 20, 2003 IP113F-DS-R02
IP113F
Preliminary Data Sheet
1. PIN Description
Type I O IPL IPH Input pin Output pin Input pin with pull-hi resistor Input pin with pull-low resistor Description
Pin no.
Label
Type I O O TP receive TP transmit
Description
Transceiver 5, 6 RXIP, RXIM 8, 9 2 TXOP, TXOM BGRES
Band gap resistor It is connected to GND through a 6.19k (1%) resistor in application circuit. 100Base-FX signal detect Fiber signal detect. It is an input signal from fiber MAU. Fiber signal detect is active if the voltage on FXSD is higher than the threshold voltage, which is 1.35v 5% when VCC is equal to 2.5v. Fiber receiver data pair Fiber transmit data pair
18
FXSD
I
13, 14 16, 17
FXRDP, FXRDM FXTDP, FXTDM
I O
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IP113F
Preliminary Data Sheet
1. PIN Description (continued)
Pin no. LED pins 31 Label LED_TP_LINK Type O Description TP port link LED On: link ok, Off: link fail, Flash: link ok & activity (Flash: on for 20ms and off for 80ms) TP port speed LED On: 100M, Off: 10M TP port full duplex LED On: full, Off: half, Flash: half & collision happens (Flash: on for 20ms and off for 80ms) Fiber port link LED On: link ok, Off: link fail, Flash: link ok & activity (Flash: on for 20ms and off for 80ms) Fiber port full duplex LED On: full, Off: half, Flash: half & collision happens (Flash: on for 20ms and off for 80ms) Fiber port signal detect On: fiber signal detected, Off: fiber unplugged Far end fault pattern received For End Fault Patterns Receive LED On: 80ms, LED Off: 20ms For End Fault Pattern not Receive LED always Off LED for link status of TP port of remote IP113F When AUTO_TEST is logic low, On: link ok, Off: link fail When AUTO_TEST is pulled high, it is always flash in a period of 100ms (On: 80ms, Off: 20ms) LED for speed of TP port of remote IP113F When AUTO_TEST is logic low, On: 100M, Off: 10M When AUTO_TEST is pulled high, On: loop back test complete, Off: during loop back test
33 32
LED_TP_SPD LED_TP_FDX
O O
36
LED_FX_LINK
O
37
LED_FX_FDX
O
38 30
LED_FX_SD LED_FX_FEF_DET
O O
29
LED_RMT_TP_LINK
O
25
LED_RMP_TP_SPD
O
LED for full duplex of TP port of remote IP113F When AUTO_TEST is logic low, On: full, Off: half When AUTO_TEST is pulled high, On: loop back test ok, Off: loop back test fail Note: The output of LED pin is logic low when the LED is on.
24
LED_RMT_TP_FDX
O
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IP113F
Preliminary Data Sheet
1. PIN Description (continued)
Pin no. Label Type Description
LED pins used as initial setting mode during reset 29 X_EN IPH IEEE 802.3X enable on TP port and fiber port 1: enable (default), 0: disable 24 TP_FORCE IPL Local TP port auto negotiation enable 1: TP port supports auto-negotiation with limited capability defined in SPEED_MODE and DUPLEX_MODE. 0: TP port supports auto-negotiation with 10M/100M, full/ half capability (default) The default value may be updated by either programming EEPROM register 3.5 or MII register 20.13. 38 SPEED_MODE IPH Local TP port speed 1: TP port has the 100Mb speed ability 0: TP port has the 10Mb speed ability only It is valid only if TP_FORCE is enabled. 30 DUPLEX_MODE IPH Local TP port duplex 1: TP port has the Full duplex ability 0: TP port has the Half duplex ability only It is valid only if TP_FORCE is enabled. 25 AUTO_SEND IPL Auto send the status to the remote IP113F 1: enable 0: disable (default) Set the duplex of fiber port 1: full duplex (default) 0: half duplex Auto loop back test 1: enable When IP113F detects a low-to-high transition on this pin, it will perform loop back test for once. 0: disable (default)
36
FX_FULL
IPH
3
AUTO_TEST
IPL
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IP113F
Preliminary Data Sheet
1. PIN Description (continued)
Pin no. Label Type Description
LED pins used as initial setting mode during reset 33 TWO_FIBER IPL Two fiber ports 1: IP113F supports two-fiber ports mode. Both port 1 and port 2 are fiber ports. RXIP and RXIM are used as FXRDP and FXRDM for the second fiber port. TXOP and TXOM are used as FXTDP and FXTDM for the second fiber port. A special requirement for the fiber MAU of port1 in this application is that the output of FXRDP and FXRDM should have no incoming signals when fiber is unplugged. For some fiber MAUs, there are amplified noisy signals on FXRDP and FXRDM when fiber is unplugged. These amplified noisy signals, which include coupled idle patterns from FXTDP and FXTDM will cause the LEDs of port1 malfunction Generally, a 3.3-V small form factor type fiber MAUs (e.g. Agilent HFBR-5903) can meet this special requirement, but 5-V duplex-SC and -ST type fiber MAUs cannot. Port2 is not limited by this special requirement. 0: IP113F supports one fiber port and one TP port. Port 1 is a TP port and port 2 is a fiber port.
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IP113F
Preliminary Data Sheet
1. PIN Description (continued)
Pin no. Label Type IPL Description Link fault pass through (LFP) 1: enable Link status of one port is forwarded to the other port. 0: disable (default) DIRECT_ FAST_F Function WIRE WD 0 0 Store and forward switch mode (default) 0 1 1 1 0 1 Modified cut-through switch mode Converter mode Converter mode with auto-change-forward function
MC operation mode 21 LFP
22 23
DIRECT_WIRE FAST_FWD
IPL
Store and forward switch mode: IP113F begins to forward a frame at the end of receiving a frame completely. Modified cut-through switch mode: IP113F begins to forward a frame after the first 64 bytes data received. TP port should be forced at 100M at this mode. Converter mode: Incoming frames are not buffered in IP113F to achieve the min latency. TP port should be forced at 100M at this mode. Converter mode with auto-change-forward function: IP113F will change forward mode itself if it detects the speed is different in TP port and FX port. In converter mode, IP113F forwards IEEE802.3x pause frame directly. In the other modes, IP113F doesn't forward IEEE802.3x pause frame directly, it sends out pause frame when its internal buffer is full.
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Aug. 20, 2003 IP113F-DS-R02
IP113F
Preliminary Data Sheet
1. PIN Description (continued)
Pin no. Label Type I, IO Description SMI interface The external MAC device uses the interface to program IP113F. MDIO is an open drain. PHY address The external MAC device uses the address to identify each IP113F in a chassis. IP113F also uses ADDR[2:0] as EEPROM address A[2:0] to read EEPROM.
SMI interface 47, 48 MDC, MDIO
31, 32, 37, 12, 46
ADDR[4:0]
IPL
Pin no.
Label
Type IPH, O EEPROM interface
Description
EEPROM interface 45, 46 SDA, SCL
Pin no. Misc. 28 41, 40
Label RESETB OSCI, X2
Type I I, O Reset It is low active. Crystal pins
Description
OSCI and X2 are connected to a 25Mhz crystal. If a 25MHz oscillator is used, OSCI is connected to the oscillator's output and X2 should be left open.
26, 27
TSM, TSE
IPL
Scan pins These two pins should be left open or connected to ground for normal operation. Interrupt 0: an interrupt happens. Its output is low. 1: no interrupt. Its output is high impedance and it needs an external pull up resistor.
15
INTB
O
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IP113F
Preliminary Data Sheet
2. Functional Description
Data forwarding IP113F supports three types of data forwarding mode, store & forward mode, modified cut-through mode and pure converter mode. It can forward a frame despite of its address and CRC error. IP113F begins to forward the received data when it receives the frame completely. The latency depends on the packet length. Modified cut-through mode IP113F begins to forward the received data when it receives the first 64 bytes of the frame. The latency is about 512 bits time width. The maximum packet length is up to1600 bytes in this mode. Please refer to pin description of FAST_FWD for configuration information. Pure converter mode IP113F operates with the minimum latency in this mode. The transmission flow does not wait until entire frame is ready, but instead it forwards the received data immediately after the data being received. Both transceivers are interconnected via internal MIIs and the internal switch engine and data buffer are not used. TP port should be forced at 100M in this application. The packet length is not limited at this mode. Please refer to pin description of DIRECT_WIRE for configuration information. Fragment forwarding IP113F forwards CRC error packets but it will filter fragments when it works in modified cut-through mode. IP113F forwards fragments if user turns on bit 3 of MII register 20. TP port force mode The TP port of IP113F can work at auto mode or force mode. The following table shows all of the combination of its TP port. TP_FORCE
0 0 0 0 1 1 1 1
SPEED_MODE
1 1 0 0 1 1 0 0
DUPLEX_MODE
1 0 1 0 1 0 1 0
IP113F's capability
100/10M, Full/Half with auto-negotiation 100/10M, Half with auto-negotiation 10M, Full/Half with auto-negotiation 10M, Half with auto-negotiation 100M, Full with auto-negotiation 100M, Half with auto-negotiation 10M, Full with auto-negotiation 10M, Half with auto-negotiation
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IP113F
Preliminary Data Sheet
Remote management IP113F supports remote monitor and configuration function. IP113F implement the function by exchanging maintenance frames on fiber ports between two IP113Fs. The maintenance frames are not forwarded to TP ports. The frame format follows the TS-1000 standard. Maintenance frame format at MII
TXD0 TXD1 TXD2 TXD3
TXEN
F0 F1 F2 F3
F4 F5 F6 F7
C0 C4 C8 C12 S0 C1 C5 C9 C13 S1 C2 C6 C10 C14 S2 C3 C7 C11 C15 S3
S4 S8 S12 M0 M4 M8 M12 M16 M20 M24 M28 M32 M36 M40 M44 E0 E4 S5 S9 S13 M1 M5 M9 M13 M17 M21 M25 M29 M33 M37 M41 M45 E1 E5 S6 S10 S14 M2 M6 M10 M14 M18 M22 M26 M30 M34 M38 M42 M46 E2 E6 S7 S11 S15 M3 M7 M11 M15 M19 M23 M27 M31 M35 M39 M43 M47 E3 E7
Bit definition of maintenance frame Bit F7 - F0 C0 C1 Item Preamble Discriminator for the maintenance signal Direction 01010101 0 0: terminal MC central MC 1: central MC terminal MC (MC: media converter) 00: Reserved 10: Indication 01: Request 11: Acknowledge 0000 00 00 00 01 : Loop test starts 00 00 00 00 : Loop test ends 00 00 00 10 : Status notice addr[4:0] RW 11 : IP113F R/W reg. 0: normal, 1: power off 0: normal, 1: abnormal 0: link up, 1: link down If S11="1", S2="X" 0: normal, 1: abnormal 0: maintenance frame 1: Far end fault indication 0: normal mode, 1: under loop test Fixed Description Note Fixed Fixed
C3 - C2
Command
C7 - C4 C15 - C8
Version Control signal
S0 S1 S2 S3 S4 S5
Condition of power Situation of receiving optical power Terminal/ network side link MC (media converter) fails Informing way for optical receiving power off Status indication for loop test
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IP113F
Preliminary Data Sheet
Bit definition of maintenance frame (continued) Bit S6 Item Information for notice of terminal link status (Available for option B or not) Terminal link speed Description 0: terminal IP113F does not support option B. 1: terminal IP113F supports option B, which can inform speed, duplex, and auto-negotiation in terminal IP113F. If S11 = "1", S6="X' 00: 10 Mbps 01: 100 Mbps 10: 1000 Mbps 11: others It is valid, if S6 = "1". If S2 or S11 = "1", S7, S8 = {X, X} 1: full duplex, 0: half duplex It is valid, if S6 = "1". If S6 ="0", S9="0". If {S7, S8} = {1,1}, S9="X" If S2 or S11 = "1", S9="X" 1: available, 0: un-available It is valid, if S6 = "1". If S6 ="0", S10="0". If {S7, S8} = {1,1}, S10="X" If S11 = "1", S10="X" 0: one UTP 1: more than one UTP Vender code for TTC standard It is C30900h. Specified by vender It is 000000h. CRC - 8 FCS calculation area: C0 - M47 Note
S8 - S7
S9
Duplex for the terminal side
S10
Auto-negotiation capability for the terminal side
S11 S15 - S12 M23 - M0 M47 - M24 E7 - E0
Number of interface in Terminal/ network side Reserved Vender code Model number FCS
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IP113F
Preliminary Data Sheet
Remote monitor Refer to the diagram below, users can instruct central IP113F, on the right, to issue a status request frame to get status defined in TS-1000 by programming MII register 24. The terminal IP113F, on the left, receives the status request frame and sends out its current status as a response frame onto the fiber port when it is available. The central IP113F receives the status frame and stores the status of terminal IP113F to its MII register 23. An acknowledge maintenance frame is store to MII register 26~30. The status of terminal IP113F is shown on the LEDs of central IP113F.
(1)
TP
IP113F (terminal)
Maintenance frame (C1=1, C2-3=10, C8-15=01000000)
FX
Maintenance frame (C1=0, C2-3=11, C8-15=01000000) (2)
IP113F (central)
(MII reg 24, 23)
TP
MDC, MDIO
Remote control read Users can instruct central IP113F to issue a remote control read frame to read the MII register of terminal IP113F by programming MII register 24. The bits [11:7] of the register 24 are filled with the address of register and bits [6:4] of the register 24 are filled with "011". The terminal IP113F receives the frame and sends out the content of the MII register to central IP113F when it is available. The central IP113F receives the frame and stores the data to MII register 27. An acknowledge maintenance frame is stored to MII register 26~30. The status of terminal IP113F is shown on LED of central IP113F.
IP113F (terminal)
Maintenance frame (C1=1, C2-3=10, C8-15=110xxxxx)
TP
FX
Maintenance frame (C1=0, C2-3=11, C8-15=01000000)
IP113F (central)
(MII reg 24,27)
TP
MDC, MDIO
Remote control write Users can instruct central IP113F to issue a configure frame to write the MII register of terminal IP113F by programming MII register 24 and 25. The bits [11:7] of the register 24 are filled with the address of register and bits [6:4] of the register 24 are filled with "111". MII register 25 defines the data. The terminal IP113F receives the configure frame, configures itself according to the content of the frame and sends out its current status as a response frame onto the fiber port when it is available. The status of terminal IP113F is shown on LED of central IP113F.
TP
IP113F (terminal)
Maintenance frame (C1=1, C2-3=10, C8-15=111xxxxx)
FX
Maintenance frame (C1=0, C2-3=11, C8-15=01000000)
IP113F (central)
(MII reg 24,25)
TP
MDC, MDIO
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IP113F
Preliminary Data Sheet
Loop back test IP113F supports two kind of loop back test function, in-band loop back test and out-band loop back test. Out-band loop back test Users can instruct central IP113F to issue a maintenance frame onto the fiber port by programming MII register 24 to request a loop back test. Central IP113F does not generate test frames and users need an external packet source from PC.
1. Disconnect switch port and instruct the terminal IP113F to perform loop back and disable terminal T2 timer by programming central IP113F through SMI
(1)
IP113F (terminal) TP
Maintenance frame (C1=1, C2-3=10, C8-15=10000000)
FX
(2)
IP113F (central)
(MII reg 24)
TP Switch
Maintenance frame (C1=0, C2-3=11, C8-15=10000000)
MDC, MDIO
2. Terminal IP113F runs at loop back mode TP Switch
IP113F (terminal) TP
(MII reg 0.14=1)
FX
IP113F (central)
3. PC forces test frames to central IP113F and terminal IP113F loops back the frames. test frame FX test frame
IP113F (terminal) TP
(MII reg 0.14=1)
IP113F (central)
TP
PC
4. PC reports the loop back test result after sending all test frames.
IP113F (terminal) TP
(MII reg 0.14=1)
FX
IP113F (central)
TP PC
5. Reconnect switch and instruct the central IP113F to end loop back test and enable T2 timer.
(1) Maintenance frame (C1=1, C2-3=10, C8-15=00000000)
IP113F (terminal) TP
FX
(2)
IP113F (central)
(MII reg 24)
TP Switch
Maintenance frame (C1=0, C2-3=11, C8-15=00000000)
MDC, MDIO
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Aug. 20, 2003 IP113F-DS-R02
IP113F
Preliminary Data Sheet
Loop back test (continued) In-band loop back test Besides performing the loop back test with an external packet source, IP113F supports an easy alternative. IP113F sends out private maintenance frame to do loop back test. All users have to do is to program MII registers through SMI.
1. Disabe receive function of central TP port and instruct the terminal IP113F to perform loop back and disable T2 timer by programming central IP113F through SMI IP113F (terminal) TP
Maintenance frame (C1=1, C2-3=10, C8-15=10000000)
FX
IP113F (central)
(MII reg 24)
TP Switch
MDC, MDIO
2. Terminal IP113F runs at loop back mode and acknowledges with maintenance frame IP113F (terminal) TP
(MII reg 0.14=1) Maintenance frame (C1=0, C2-3=11, C8-15=10000000)
FX
IP113F (central)
TP
Switch
3. Central IP113F forces test frames to terminal IP113F and terminal IP113F loops back the test frames. Central IP113F checks the received test frame. IP113F (terminal) TP
(MII reg 0.14=1)
test frame FX test frame
IP113F (central)
(MII reg 24,25)
TP
Switch
MDC, MDIO
4. Central IP113F ends loop back test enables receive function of TP port and enable LP T2 timer
(1) Maintenance frame (C1=1, C2-3=10, C8-15=00000000)
IP113F (terminal) TP
FX
(2)
IP113F (central)
(MII reg 24)
TP Switch
Maintenance frame (C1=0, C2-3=11, C8-15=00000000)
MDC, MDIO
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Aug. 20, 2003 IP113F-DS-R02
IP113F
Preliminary Data Sheet
Loop back test (continued) Programming procedure for In-band loop back test Step Description 1 Set local IP113F TP receive disabled 2a 2 3 4 5 6 C1 C3~C2 01 01 -1 -01 --C15~C8 11 11 11 11 00 00 00 01 -11 01 10 11 --Note Set Reg. 20.14 off Reg24 and Reg 25 TS-1000: loop back set -Reg24 and Reg 25 --
Set remote T2 timer disabled by 1 maintenance frame Set remote IP113F to be loop back mode 1 enabled by maintenance frame Remote IP113F sends back loop back acknowledge Send loop back test maintenance frame Remote IP113F send back acknowledge Local IP113F stores the loop back maintenance to Reg. 26~30 and checks CRC bit is in Reg. 26.12 Repeat step 4~6 continuously Set remote IP113F to be loop back mode 1 disable by maintenance frame Remote IP113F sends back loop back acknowledge Set local IP113F TP receive enable --
7 8 9 10
-01 -00 00 00 00 -TC-1000: loop back end -Set Reg. 20.14 on
Auto in-band loop back test Step 1 1.1 1.2 1.3 1.4 1.5 2 3 Description Set pin AUTO_TEST to "1" (The following step is executed automatically by IP113F) Central IP113F sends loop back start request to remote IP113F and goes to CST2 state. Remote IP113F sends loop back start acknowledge to Central IP113F and enters loop back test mode. Central IP113F goes to CST1 state and begins sending 15 frames in 64 bytes. Remote IP113F loops back the received frames at the TP port's PMD sub-layer. Central IP113F checks the loop back frames and reports the result. The LED pin LED_RMT_TP_LINK is Flash (on 80ms / off 20ms) during the auto loop back test period (AUTO_TEST is "1"). The LED pin LED_RMT_TP_SPD indicates the loop back test complete (on) (when AUTO_TEST is "1"). The LED pin LED_RMT_TP_FDX indicates the loop back test ok (on) (when AUTO_TEST is "1") If another auto loop back test is needed, set AUTO_TEST to "0" and then "1". That is, AUTO_TEST is triggered whenever there is a low-to-high transition on this pin.
4
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Aug. 20, 2003 IP113F-DS-R02
IP113F
Preliminary Data Sheet
Remote monitor without SMI programming Auto sends (Status change notice) IP113F sends out status frame without receiving status request frame if pin AUTO_SEND is pulled high. It sends out the first status frame onto the fiber port when the link status of fiber port has established. It sends out status frames when the status on TP port has changed. IP113F supports two types of frame. For a TS-1000 maintenance frame, C[9:8] is 2'b10 and S[15:0] is defined as that in TS-1000 standard. For an ICplus maintenance frame, C[9:8] is 2'b11 and S[15:0] is the content of MII register 22. It carries ICplus private defined information. User can select the frame type by programming MII register 20.10. Central IP113F uses the mechanism to get the status of the remote IP113F even if there is no SMI programming. Option A Central IP113F sends indication frames to terminal IP113F if its status is changed.
IP113F (terminal) TP
Maintenance frame (C1=1, C2-3=01, C8-9= 01)
IP113F (central) TP status changed !!
FX
Option B Terminal IP113F sends indication frames to central IP113F if its status is changed.
IP113F (terminal) TP status changed !!
Maintenance frame (C1=0, C2-3=01, C8-9= 01)
IP113F (central) TP
FX
CRC polynomial for maintenance frame: X8 + X2 + X + 1
data in CRC + data X0 X1 X2 X3 X4 X5 X6 X7
CRC calculation
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Aug. 20, 2003 IP113F-DS-R02
IP113F
Preliminary Data Sheet
Link fault pass through When link fault pass through function is enabled, link status on TX port will inform the FX port of the same device and vice versa. From the link fault pass through procedure illustrates in the figure below, if link fail happens on IP113F's TX port (1), the local FX port sends non-idle pattern to notice the remote FX port (2). The remote FX port then forces its TX port to link failed after receiving the non-idle pattern (4). In other words, this mechanism will alert the link fault status of local TX port to the remote converter's TX port, and the link status of the remote TX port will become off. Link status LED will also be off for both IP113F and its link partner.
(3) fiber port gets remote link fault information local Switch1 or NIC 1 UTP IP113F remote IP113F (5) remote TP link is off
(1) TP port link failed
Fiber
UTP
Switch2 or NIC 2 link off
(2) fiber port sends non-idle pattern
(4) TP link fail
The procedure of link fault pass through
Normal case
remote Switch1 LED SW1 UTP IP113F Fiber IP113F UTP local Switch2 LED SW2
LED_TP_LINK1 LED_FX_LINK1
LED_FX_LINK2 LED_TP_LINK2
Link LED on SW1 LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Link LED on SW2 ON ON ON ON ON ON
Remote TP port disconnected
remote Switch1 LED SW1 UTP disconnected IP113F Fiber UTP IP113F
LED_FX_LINK2 LED_TP_LINK2
local Switch2 LED SW2
LED_TP_LINK1 LED_FX_LINK1
Link LED on SW1 LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Link LED on SW2 Off Off Off Off Off Off
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IP113F
Preliminary Data Sheet
FX port disconnected
remote Switch1 LED SW1 UTP IP113F Fiber IP113F UTP local Switch2 LED SW2
LED_TP_LINK1 LED_FX_LINK1
LED_FX_LINK2 LED_TP_LINK2
Link LED on SW1 LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Link LED on SW2 Off Off Off Off Off Off
LED diagnostic functions for fault indication LED_TP_LINK On Flash Off Off Off LED_FX_LINK On Flash Off Off Off LED_FX_SD On On On Off On LED_FX_FEF_DET Off Off Off Off Flash Status Link ok Link ok & activity Remote TP link off Fiber RX off, Fiber TX/ RX off Fiber TX off
Note Flash: flash, period 100 ms Link fault pass through is enabled.
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IP113F
Preliminary Data Sheet
EEPROM - store the initial value IP113F supports two ways to load initial value of MII registers. The procedure is illustrated as below.
1. IP113F reads the default setting of MII register from pins
IP113F pins
2. IP113F updates the default setting of MII by reading EEPROM. If there exists an EEPROM.
EEPROM
IP113F
3. After reading EEPROM, IP113F is virtually isolated from the EEPROM. Micro-controller can program both MII register and EEPROM.
EEPROM
uC
SCL, SDA
IP113F
MDC, MDIO
4. IP113F reloads the content of EEPROM to recover the value in MII registers programmed by Micro-controller after power on reset.
EEPROM
IP113F
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IP113F
Preliminary Data Sheet
Auto MDI_MDIX IP113F supports auto MDI-MDIX. It is always enabled. The following is its application circuit for auto MDI-MDIX.
RXIP RXIM RD + RD AVCC TXOP TXOM TD + TD AVCC
IP113F 50 50
IP113F
CT
50
50
CT
MDI-MDIX 0.1u transformer 0.1u
MDI-MDIX transformer
GND
GND
IP113F's application circuit (auto MDI-MDIX on)
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Aug. 20, 2003 IP113F-DS-R02
IP113F
Preliminary Data Sheet
Serial management interface User can access IP113F's MII registers through serial management interface MDC and MDIO. A specific pattern on MDIO is used to access a MII register. Its format is shown in the following table. When the SMI is idle, MDIO is in high impedance. To initialize the MDIO interface, the management entity sends a sequence of 32 contiguous "1" and "start" on MDIO.
Syatem diagram 113F
MDC MDIO
113F
MDC MDIO
113F
MDC MDIO
management entity
Frame format Read Operation Write Operation
<IP113F's address> <01><10> <01><01><10>
MDC
z z
MDIO
1..1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 op A A A A A R R R R R TA b b b idle start code 4321043210 111 write PHY address = Reg address = 543 01h 00h
1 b 1 2
0 b 1 1
0 1 1 0 0 0 0 0 0 0 0 1..1 b b b b b b b b b b b idle 19876543210 0 Register data
MDC MDIO
z z z
1..1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1..1
idle
start
op code read
A A A A A R R R R R TA b b b b b b b b b b b b b b b b 4321043210 1111119876543210 PHY address = Reg address = 543210 Register data 01h 00h
idle
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IP113F
Preliminary Data Sheet
MII registers Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Control Control Register Status Register PHY identifier Register 1 PHY identifier Register 2 AN Advertisement Register AN Link Partner Base Page Ability Register AN Expansion Register (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Special Control Register Interrupt Register Extended Status Register Statistic Counter Register Switch Configuration Register 1 Switch Configuration Register 2 Local Switch Extended Register Link Partner Switch Extended Status Register Remote Control Transmit Register 1 Remote Control Transmit Register 2 Remote Control Receive Register 1 Remote Control Receive Register 2 Remote Control Receive Register 3 Remote Control Receive Register 4 Remote Control Receive Register 5 Switch Configuration Register 3 NWAY NWAY NWAY SWITCH SWITCH SWITCH SWITCH SWITCH RMC RMC RMC RMC RMC RMC RMC SWITCH Register Name NWAY NWAY NWAY NWAY NWAY NWAY NWAY
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IP113F
Preliminary Data Sheet
The basic MII registers Type R/W SC RO Pin(1) Description Read/Write Self-Clearing Read Only The default value is "1" and it depends on the setting of its corresponding pin. NAME R/W Type RC LL LH Pin(0) Description Read and Clear Latching Low Latching High The default value is "0" and it depends on the setting of its corresponding pin. DEFAULT 0
MII
DESCRIPTION 1 = PHY reset 0 = normal operation This bit is self-clearing, IP113F will return a value of 1 before reset process is completed, and will not accept any write transaction of MII Management within reset process. Make any change to Auto-Negotiation or speed mode will cause IP113F reset again. 1 = Loopback mode 0 = normal operation When this bit is set, IP113F will be isolated from the network media, and the assertion of TXEN at the MII will not transmit data on the network. All MII transmit data path will return to MII receive data path in response to the assertion of TXEN. MII COL signal will remain de-asserted at all times, unless bit 0.7 (Collision Test) is set. Use has to wait about 100ms for loop back path ready. 1 = 100Mbps 0 = 10Mbps It is valid only if bit 0.12 is set to be 0. 1 = Auto-Negotiation Enable 0 = Auto-Negotiation Disable MII register 16.11 auto-MDI/MDIX should be disabled if auto-negotiation is disabled. 1 = power down 0 = normal operation Setting this bit to 1 will cause IP113F into power down mode, but still respond to management transactions. 1 = electrically isolate PHY from MII 0 = normal operation When this bit is setting to 1, IP113F will be isolated from RMII, and not respond to the TXD[3:0] and TXEN and keep CRS, RXDV and RXD[3:0] in high impedance, but will respond to management transactions. If PHY address of IP113F is setting to 0 at power-on reset, this bit will be set to 1, otherwise will be set to 0.
MII control register (address 00h) 0.15 Reset R/W SC
0.14
Loopback
R/W
0
0.13
Speed Selection
RW
Pin(1)
0.12
Auto-Negotiation Enable
RW
1
0.11
Power Down
R/W
0
0.10
Isolate
R/W
0
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IP113F
Preliminary Data Sheet
The basic MII registers (continued) MII NAME R/W DESCRIPTION DEFAULT
MII control register (address 00h) 0.9 Restart AutoNegotiation RW 1 = re-starting Auto-Negotiation 0 = Auto-Negotiation re-start complete Setting this bit to logic high will cause IP113F to restart an Auto-Negotiation cycle, but depend on the value of bit 0.12 (Auto-Negotiation Enable). If bit 0.12 is cleared then this bit has no effect, and change to Read Only. When an Auto-Negotiation cycle is being processed, write 0 into this bit has no effect. This bit is self-clearing after Auto-Negotiation process is completed. 1 = full duplex 0 = half duplex It is valid only if bit 0.12 is set to be 0. 1 = enable the collision test 0 = disable the collision test If setting this bit to logic 1, when MII TXEN signal is asserted, IP113F will assert the MII COL signal within 512BT (Bit Time, depend on 10Mbps or 100Mbps). When MII TXEN is de-asserted, then TP110 will assert MII COL signal within 4BT. Clearing this bit to logic 0 for normal operation Write as 0, ignore on read 0
0.8
Duplex mode
R/W
Pin(1)
0.7
Collision test enable
R/W
0
0[6:0]
Reserved
R/W
-
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IP113F
Preliminary Data Sheet
The basic MII registers (continued) MII NAME R/W DESCRIPTION DEFAULT
MII status register (address 01h) 1.15 100Base-T4 capable RO 1 = 100Base-T4 capable 0 = not 100Base-T4 capable IP113F does not support 100Base-T4. This bit is fixed to be 0. 1 = 100Base-X full duplex capable 0 = not 100Base-X full duplex capable The default of this bit will change depend on the external setting of IP113F. If external pin setting without 100Base-X full duplex support, then this bit will change default to logic 0. 1 = 100Base-X half duplex capable 0 = not 100Base-X half duplex capable The default of this bit will change depend on the external setting of IP113F. If external pin setting without 100Base-X half duplex support, then this bit will change default to logic 0 1 = 10Base-T full duplex capable 0 = not 10Base-T full duplex capable The default of this bit will change depend on the external setting of IP113F. If external pin setting without 100Base-T full duplex support, then this bit will change default to logic 0 1 = 10Base-T half duplex capable 0 = not 10Base-T half duplex capable The default of this bit will change depend on the external setting of IP113F. If external pin setting without 100Base-X full duplex support, then this bit will change default to logic 0 Ignore on read 1 = preamble may be suppressed 0 = preamble always required 1 = Auto-Negotiation complete 0 = Auto-Negotiation in progress When read as logic 1, indicates that the Auto-Negotiation process has been completed, and the contents of register 4, 5, 6 and 7 are valid. When read as logic 0, indicates that the Auto-Negotiation process has not been completed, and the contents of register 4, 5, 6 and 7 are meaningless. If Auto-Negotiation is disabled (bit 0.12 set to logic 0), then this bit will always read as logic 0. 0
1.14
100Base-X full duplex Capable
RO
1
1.13
100Base-X half duplex Capable
RO
1
1.12
10Base-T full duplex Capable
RO
1
1.11
10Base-T half duplex Capable
RO
1
1[10:7] 1.6 1.5
Reserved MF preamble Suppression Auto-Negotiation Complete
RO RO RO
1 0
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IP113F
Preliminary Data Sheet
The basic MII registers (continued) MII NAME R/W DESCRIPTION DEFAULT
MII status register (address 01h) 1.4 Remote fault RO LH 1 = remote fault detected 0 = not remote fault detected When read as logic 1, indicates that IP113F has detected a remote fault condition. This bit is set until remote fault condition gone and before reading the contents of the register. This bit is cleared after IP113F reset. 1 = Auto-Negotiation capable 0 = not Auto-Negotiation capable When read as logic 1, indicates that IP113F has the ability to perform Auto-Negotiation. The value of this bit will depend on the external mode setting of IP113F operation mode. 1 = Link Pass 0 = Link Fail When read as logic 1, indicates that IP113F has determined a valid link has been established. When read as logic 0, indicates the link is not valid. This bit is cleared until a valid link has been established and before reading the contents of this registers. 1 = jabber condition detected 0 = no jabber condition detected When read as logic 1, indicates that IP113F has detected a jabber condition. This bit is always 0 for 100Mbps operation and is cleared after IP113F reset. This bit is set until jabber condition is cleared and reading the contents of the register. 1 = Extended register capabilities 0 = No extended register capabilities IP113F has extended register capabilities. 0
1.3
Auto-Negotiation Ability
RO
1
1.2
Link Status
RO LL
0
1.1
Jabber Detect
RO LH
0
1.0
Extended capability
RO
1
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IP113F
Preliminary Data Sheet
The basic MII registers (continued) MII NAME R/W DESCRIPTION DEFAULT
PHY Identifier (address 02h) 2[15:0] PHY identifier RO IP113F OUI (Organizationally Unique Identifier) ID, the msb is 3rd bit of IP113F OUI ID, and the lsb is 18th bit of IP113F OUI ID. IP113F OUI is 0090C3. 0243h
MII
NAME
R/W
DESCRIPTION IP113F OUI ID, the msb is 19th bit of IP113F OUI ID, and lsb is 24th bit of IP113F OUI ID. TP110 model number IP113F revision number
DEFAULT
PHY Identifier (address 03h) 3[15:10] 3[9:4] 3[3:0] PHY identifier Manufacture's Model Number Revision Number RO RO RO 3h 6h 0
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IP113F
Preliminary Data Sheet
The basic MII registers (continued) MII NAME R/W DESCRIPTION DEFAULT
Auto-Negotiation Advertisement register (address 04h) 4.15 Next Page RO 1 = Next Page ability is supported 0 = Next Page ability is not supported IP113F does not support next page, this bit is fixed to be 0. Reserved by IEEE, write as 0, ignore on read 1 = Advertises that this device has detected a remote fault 0 = No remote fault detected Reserved for future IEEE use, write as 0, ignore on read 1 = Advertises that this device has implemented pause function 0 = No pause function supported 1 = 100BASE-T4 is supported 0 = 100BASE-T4 is not supported 1 = 100BASE-TX full duplex is supported 0 = 100BASE-TX full duplex is not supported 1 = 100BASE-TX is supported 0 = 100BASE-TX is not supported 1 = 10BASE-T full duplex is supported 0 = 10BASE-T full duplex is not supported 1 = 10BASE-T is supported 0 = 10BASE-T is not supported Use to identify the type of message being sent by Auto-Negotiation. 0
4.14 4.13
Reserved Remote Fault
RW R/W
0 0
4[12:11] 4.10
Reserved Pause
RO RW
0 Pin(0)
4.9 4.8 4.7 4.6 4.5 4[4:0]
100BASE-T4 100BASE-TX full duplex 100BASE-TX 10BASE-T full duplex 10BASE-T Selector Field
RW R/W R/W R/W R/W RO
0 Pin(1) Pin(1) Pin(1) Pin(1) 00001
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IP113F
Preliminary Data Sheet
The basic MII registers (continued) MII NAME R/W DESCRIPTION DEFAULT
Link partner ability register (address 05h) Base Page 5.15 5.14 5.13 Next Page Acknowledge Remote Fault RO RO RO 1 = Next Page ability is supported by link partner 0 = Next Page ability is not supported by link partner 1 = Link partner has received the ability data word 0 = Not acknowledge 1 = Link partner indicates a remote fault 0 = No remote fault indicate by link partner If this bit is set to logic 1, then bit 1.4 (Remote fault) will set to logic 1. Reserved by IEEE for future use, write as 0, read as 0. 1 = Link partner support 100BASE-T4 0 = Link partner is not support 100BASE-T4 1 = Link partner support 100BASE-TX full duplex 0 = Link partner is not support 100BASE-TX full duplex 1 = Link partner support 100BASE-TX 0 = Link partner is not support 100BASE-TX 1 = Link partner support 10BASE-T full duplex 0 = Link partner is not support 10BASE-T full duplex 1 = Link partner support 10BASE-T 0 = Link partner is not support 10BASE-T Protocol selector of the link partner 0 0 0
5[12:10] 5.9 5.8
Reserved 100BASE-T4 100BASE-TX full duplex 100BASE-TX 10BASE-T full duplex 10BASE-T Selector Field
RO RO RO
0 0 0
5.7 5.6 5.5 5[4:0]
RO RO RO RO
0 0 0 00000
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IP113F
Preliminary Data Sheet
The basic MII registers (continued) MII NAME R/W DESCRIPTION DEFAULT
Auto-Negotiation Expansion register (address 06h) 6[15:5] 6.4 Reserved Parallel Detection Fault RO RO LH Reserved by IEEE, writes as 0, ignore on read. 1 = A fault has been detected via Parallel Detection function 0 = A fault has not detected via Parallel Detection function 1 = Link Partner is Next Page able 0 = Link Partner is not Next Page able 1 = Local Device is Next Page able 0 = Local Device is not Next Page able 1 = A New Page has been received 0 = A New Page has not been received 1 = Link Partner is Auto-Negotiation able 0 = Link Partner is not Auto-Negotiation able 0 0
6.3 6.2 6.1 6.0
Link Partner Next Page Able Next Page Able Page Received Link Partner Auto-Negotiation Able
RO RO RO LH RO
0 0 0 0
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IP113F
Preliminary Data Sheet
Extended MII registers and EEPROM registers MII ROM NAME R/W DESCRIPTION DEFAULT 55
EEPROM enable register 0 (EEPROM register 00D) -0[7:0] RO EEPROM enable register 0 This register should be filled with 55. IP113F will examine the specified pattern to confirm if there is a valid EEPROM.
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT AA
EEPROM enable register 1 (EEPROM register 01D) -1[7:0] RO EEPROM enable register 1 This register should be filled with AA. IP113F will examine the specified pattern to confirm if there is a valid EEPROM. The initial setting is updated with the content of EEPROM only if the specified pattern 55AA is found.
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IP113F
Preliminary Data Sheet
Extended MII registers and EEPROM registers (continued) MII ROM NAME R/W R/W DESCRIPTION ANALOG on/off (It is valid only if register 16.15=0.) 1: analog off, 0: analog on (default) Low power mode disable (It is valid only if 16.15=0.) 1: disable, 0:enable (default) REPEAT mode enable 1: enable, 0:disable (default) Bypass PCS scrambler (It is valid only if 16.15=1.) 1: bypass scrambler, 0: not bypass (default) Bypass PCS 4B/5B coder (It is valid only if 16.15=1.) 1: bypass 4B/5B, 0: not bypass (default) Bypass DSP re-start function in PCS 1: bypass DSP re-start, 0: not bypass (default) 10Mb transmit NLP enable 1: enable (default), 0:disable Analog power save mode disable 1: disable, 0: enable (default) Far-End-Fault function disable 1: disable, 0: enable (default) Jabber function enable 1: enable, 0:disable (default) Heart Beat function enable 1: enable, 0:disable (default) Auto Crossover function disable 1: disable, 0: enable (default) It should be disabled if MII register 0.12 auto-negotiation is disabled. Speed Up DSP (It is valid only if 16.15=1.) 1: enable, 0:disable (default) Speed Up Digital Simulation (It is valid only if 16.15=1.) 1: enable, 0:disable (default) DEBUG mode enable 1: enable, 0:disable (default) DEFAULT 0
Special control register (16D) 16.0 -mr_analog_off
16.1
--
mr_lpds_mode
R/W
0
16.2 16.3
---
mr_repeater_mode
R/W
0 0
mr_bypass_scramble R/W
16.4
--
mr_bypass_100x _coder mr_bypass_dsp _rst mr_tx_nlp_disable mr_analog_pwsv _disable mr_fef_disable mr_jabber_enable mr_heart_beat _enable mr_auto_cross _disable
R/W
0
16.5
--
R/W
0
16.6 16.7 16.8 16.9 16.10 16.11
-------
R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0
16.12 16.13
---
mr_speed_up_dsp mr_speed_up
R/W R/W
0 0
16.14 16.15
---
Reserved mr_debug_mode
R/W R/W
0 0
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IP113F
Preliminary Data Sheet
Extended MII registers and EEPROM registers (continued) MII ROM NAME R/W RO RC DESCRIPTION Link status change It is logic "1" when link status changes on TP port and it will active interrupt pin. It is self-clear after reading the register. 1: Interrupt occur 0: nothing happen Duplex mode change 1: Interrupt occur 0: nothing happen Speed mode change 1: Interrupt occur 0: nothing happen Maintenance frame receive indication 1: Interrupt occur 0: nothing happen Statistic counter overflow 1: Interrupt occur 0: nothing happen Interrupt status 1: Interrupt occur 0: nothing happen It is logic "OR" of 17.0~17.4. Interrupt status 1: remote link partner power abnormal 0: nothing happen Remote LP power abnormal interrupt enable 1: not mask interrupt 0: mask interrupt Mask TP port link change Interrupt 1: mask, 0: not mask (default) Mask TP port duplex mode change Interrupt 1: mask interrupt (default), 0: not mask Mask TP port speed mode change Interrupt 1: mask interrupt (default), 0: not mask Mask maintenance frame receive indication Interrupt 1: mask interrupt (default), 0: not mask Mask Statistic counter overflow Interrupt 1: mask interrupt (default), 0: not mask Mask all Interrupt 1: mask interrupt (default), 0: not mask DEFAULT 0
Interrupt register (17D) 17.0 -intr_link
17.1 17.2 17.3 17.4 17.5
------
intr_duplex intr_speed intr_mf_rx_indicate intr_cnt_overflow intr_status
RO RC RO RC RO RC RO RC RO RC RO RC RW
0 0 0 0 0
17.6
--
Intr_pwabn
0
17.7
--
Intr_pwabn_en
0
17.8 17.9 17.10 17.11
-----
intr_link_mask intr_duplex_mask intr_speed_mask intr_mf_rx_indc _mask intr_cnt_ov_mask intr_all_mask Reserved
RW RW RW RW
1 1 1 1
17.12 17.13 17[15:14]
----
RW RW RW
1 1 0
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IP113F
Preliminary Data Sheet
Extended MII registers and EEPROM registers (continued) MII ROM NAME R/W RO RO RO RO RO RO RO Jabber status 1: jabber, 0: no jabber (default) Polarity status 1: polarity error, 0: polarity ok (default) MDI/MDIX status 0: MDI, 1:MDIX TP port link Status 1: link ok, 0; link fail (default) Resolve complete 1: Nway or force mode complete, 0: not complete (default) TP port duplex mode (It is valid only if 18.11=1.) 1: full (default), 0: half TP port operation speed (It is valid only if 18.11=1.) 1: 100M (default), 0: 10M DESCRIPTION NWAY state machine DEFAULT 0 0 0 0 0 0 0
PHY extended status register (18D) 18[3:0] -an_arbit_state[3:0] 18[6:4] 18.7 18.8 18.9 18.10 18.11 ------Reserved[2:0] jabber polarity mdix_en link_real resolved
18.12 18.13
---
Reserved mr_duplex_mode
RO RO
0 1
18.14
--
mr_speed_selection
RO
1
18.15
--
Reserved
RO
0
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IP113F
Preliminary Data Sheet
Extended MII registers and EEPROM registers (continued) MII ROM NAME R/W DESCRIPTION DEFAULT 0
Statistic counter registers (MII register 19D) 19[11:0] -mg_statistic_cnt[11:0] RO Statistic Counter [11:0] Cnt_index Content of statistic counter[11:0] 3'b000 3'b001 3'b010 3'b011 3'b100 3'b101 3'b110 3'b111 19[14:12] 19.15 --cnt_index[2:0] cnt_loop_en RW RW TP port (port1) received packet count TP port (port1) received CRC error count TP port (port1) drop packet count TP port (port1) collision event count FX port (port2) received packet count FX port (port2) received CRC error count FX port (port2) drop packet count FX port (port2) collision event count
The current counter index The counter index loop enable 1: Each time reading of this register (MII register 19) will increase cnt_index[2:0] by one. The content will be loop back to "0" after reading if it is "7". 0: cnt_index[2:0] is fixed to the setting value.
0 1
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IP113F
Preliminary Data Sheet
Extended MII registers and EEPROM registers (continued) MII ROM NAME R/W DESCRIPTION DEFAULT 0
Switch configuration register 1 (MII register 20D, EEPROM register 02~03D) 20.0 2.0 mg_crossover_en R/W Select TP to be MDIX or MDI. It is valid only if MII register16.11 is disabled. 0: MDI 1: MDIX 20.1 20.2 20.3 2.1 2.2 2.3 direct_wire fast_fwd mg_pass_fragment
_en
R/W R/W R/W
Please see pin description of DIRECT_WIRE for more detail information. Please see pin description of FAST_FWD for more detail information. Pass fragment packet (>7B and <64B) 1: pass fragment 0: not pass fragment Collision 16 times drop enable 1: drop 0: not drop Collision back-off enable 1: back after collision 0: not back off after collision It must be 0. TP port backpressure control enable for half duplex 1: backpressure enable 0: backpressure disable Remote control enable (TX/RX. ability for maintenance frame) 1: ability enable 0: ability disable Auto send status frame to remote partner enable (AUTO_SEND) 1: auto send indication maintenance frame 0: disable auto send The content of auto send status frame 1: TTC (TS-1000) The frame format is defined in TS-1000. 0: ICPLUS The frame format is similar to the one defined in TS-1000 except the bit definition of S[15:0]. S[15:0] is the content of MII register 22[15:0]. Local IP113F uses the frame to indicate its status to the remote IP113F. The remote IP113F receives the frame and stores the information to the MII register 23. Informing way for optical receiving SD off 1: far end fault pattern 0: maintenance frame
Pin (0) Pin (0) 0
20.4
2.4
mg_col16_drop_en
R/W
0
20.5
2.5
mg_col_backoff _en reserved p01_mg_backpress _en
R/W
1
20.6 20.7
2.6 2.7
R/W R/W
0 1
20.8
3.0
mg_rem_ctrl_en
R/W
1
20.9
3.1
mg_auto_tx_mf_en
R/W
Pin (0)
20.10
3.2
mg_auto_tx_ttc _content
R/W
1
20.11
3.3
mg_sd_off_way
R/W
1
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IP113F
Preliminary Data Sheet
MII ROM NAME R/W DESCRIPTION DEFAULT 1 Switch configuration register 1 (MII register 20D, EEPROM register 02~03D) 20.12 3.4 mg_em_bist_en R/W SSRAM BIST enable (R/W by EEPROM only) 1: BIST enable 0: bypass BIST 20.13 3.5 tp_force R/W This pin overwrites the setting on pin 26 TP_FORCE. 20.14 3.6 mg_receive_en R/W TP receive enable 1: TP port can receive packet 0: TP port drop all received packet Fiber port link status (descramble_locked) 1: Fiber port is link 0: Fiber port is not link
Pin (0) 1
20.15
3.7
p02_link_on
RO
0
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Switch configuration register 2 (MII register 21D, EEPROM register 04~05D) 21[7:0] 4[7:0] p01_mg_port _page_no p02_mg_port _page_no R/W TP port allocated memory pages The default is 120 pages with 64 bytes per page. FX port allocated memory pages The default is 120 pages with 64 bytes per page. 120d
21[15:8] 5[7:0]
R/W
120d
Note: p01_mg_port_page_no adds p02_mg_port_page_no must be equal to 240.
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IP113F
Preliminary Data Sheet
Extended MII registers and EEPROM registers (continued) MII ROM NAME R/W DESCRIPTION DEFAULT 0
Local MC extended register (MII register 22D, EEPROM register 06~07D) 22.0 6.0 mg_loopback_en R/W Loop-back test enable (same as MII register 0.14) 1: loop back mode 0: normal mode 22.1 6.1 mg_status_rpt _en p01_mg_auto _neg_en RO TP port status available 1: TP status is valid 0: TP status is not ready TP port auto-negotiation enable (same as MII register 0.12) 1: TP auto-negotiation enable 0: TP auto-negotiation disable TP port speed selection (same as MII register 0.13) 1: 100M, 0:10M TP port duplex mode selection (same as MII register 0.8) 1: full duplex, 0:half duplex TP port flow control selection (same as MII register 4.10) 1: on, 0:off TP port link status off 1: link off, 0: link ok Fiber port flow control/backpressure enable 1: enable, 0: disable Fiber port duplex mode (FX_FULL) 1: full duplex, 0:half duplex Fiber port signal detect (power) 1: Fiber SD has been low since last read 0: Fiber SD is O.K. Fiber port Far-End-Fault detect 1: FEF has been detected since last read 0: no FEF pattern detected TP port input Rate Control 2'b00: full speed 2'b01: 1/4 speed 2'b10: 2/4 speed 2'b11: 3/4 speed TP port output Rate Control 2'b00: full speed 2'b01: 1/4 speed 2'b10: 2/4 speed 2'b11: 3/4 speed Link Fault Pass through enable (LFP) 1: enable, 0: disable
0
22.2
6.2
R/W
1
22.3
6.3
p01_mg_speed _mode p01_mg_duplex _mode p01_mg_flow _ctrl_en p01_mg_link _status p02_mg_flow _ctrl_en p02_mg_duplex _mode p02_mg_link _status p02_mg_fef _detect p01_mg_throttle _confg
R/W
Pin (1)
22.4
6.4
R/W
Pin (1)
22.5
6.5
R/W
Pin (1)
22.6 22.7 22.8 22.9
6.6 6.7 7.0 7.1
RO R/W R/W RO LL RC RO LH RC R/W
0 Pin (1) 1 1
22.10
7.2
0
22[12:1 7[4:3] 1]
00
22[14:1 7[6:5] p01_mg_throttle_co 3] nfg
R/W
00
22.15
7.7
mg_link_pass_en
R/W
Pin (0)
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IP113F
Preliminary Data Sheet
Extended MII registers and EEPROM registers (continued) MII ROM NAME R/W DESCRIPTION DEFAULT 0
Link partner MC extended status register (MII register 23D) 23.0 -lp_loopback_en RO Loop-back enable of remote LP 1: LP is in loop back mode 0: LP is in normal mode 23.1 -lp_status_rpt_en RO Option B support 1: support 0: not support TP port auto-negotiation enable 1: enable, 0:disable TP port speed selection 1: 100M, 0:10M TP port duplex mode selection 1: full duplex, 0: half duplex TP port flow control selection 1: flow control enable 0: flow control disable TP port link off 1: link off, 0:link on Fiber port flow control/backpressure enable 1: flow control enable 0: flow control disable 23.8 23.9 --lp_fb_duplex_mode lp_fb_link_status RO RO Fiber port duplex mode 1: full duplex, 0: half duplex Fiber port signal detect (power) off 1: off, 0: on MC power abnormal 1: power abnormal 0: power O.K. MC failed 1: MC is out of function 0: MC is normal Link Partner informing way of SD off 1: far end fault pattern 0: maintenance frame MC support multi-port UTP 1: more than one TP port 0: one TP port Link Fault Pass through enable 1: LFP is enable 0: LFP is disable Note
0
23.2 23.3 23.4 23.5
-----
lp_tp_autoneg_en lp_tp_speed_mode lp_tp_duplex_mode lp_tp_flow_ctrl_en
RO RO RO RO
0 0 0 0
23.6
--
lp_tp_link_off
RO
1
23.7
--
lp_fb_flow_ctrl_en
RO
0
0 0
23.10 23.11
---
reserved lp_power_abnormal
RO RO
0 0
23.12
--
lp_mc_failed
RO
0
23.13
--
lp_sd_off_way
RO
0
23.14
--
lp_multi_tp_port
RO
0
23.15
--
mg_link_pass_en
RO
0
Note: Only available when MII 20.10 = 0.
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IP113F
Preliminary Data Sheet
Extended MII registers and EEPROM registers (continued) MII ROM NAME R/W DESCRIPTION DEFAULT 0 0
Remote control Transmit register 1 (MII register 24D) 24.0 -mg_rem_tx_code R/W Remote control frame send trigger 24.1 -mg_rem_tx_code R/W Transmitted maintenance direction discriminator C1 Frame direction 0: upstream 1: downstream Transmitted maintenance frame command discriminator C3~C2 01: request 11: acknowledge 10: Indication 00: reserved Transmitted maintenance signals C15~C8 bit11 (C15) 0000 0000 0000 frame control
24[3:2]
--
mg_rem_tx_code
R/W
00
24[11:4]
--
mg_rem_tx_code
R/W
8'b0
0 0 0
bit4 (C8) 0 01: Loop test start 0 00: Loop test finished 0 10: Status indication
A4 A3 A2 A1 A0 RW 11: IP113F R/W registers
RW: 0: read, 1: write A[4:0]: register address 24[15:12] -Reserved
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT 16'b0
Remote control Transmit register 2 (MII register 25D) 25[15:0] -mg_rem_wt_data R/W Remote control write data If a remote write command is issued, that is, MII register 24[11:4] is programmed as xxxxx111. The content in this register will be embedded into S[15:0] and is sent to the remote site. The partner IP113F receives the frame (register write) and update the addressed MII register with the value defined in this register
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IP113F
Preliminary Data Sheet
Extended MII registers and EEPROM registers (continued) MII ROM NAME R/W DESCRIPTION DEFAULT 0
Remote control Receive register 1 (MII register 26D) 26.0 -mg_rem_rx_code RO Receive a acknowledge or not defined RC maintenance frame C0 1: IP113F receives a maintenance frame. 0: no maintenance frame received. User can poll this bit to make sure a there is a maintenance frame is received. It is a read and auto-clear bit. 26.1 26[3:2] 26[11:4] 26[12] ----mg_rem_rx_code mg_rem_rx_code mg_rem_rx_code mg_rem_rx_code RO RO RO RO RC Received maintenance direction discriminator C1 Received maintenance frame command discriminator C3~C2 Received maintenance frame control signals C15~C8 Received maintenance frame CRC error 1: received maintenance frame CRC error. 0: received maintenance frame CRC ok. It is a read and auto-clear bit.
0 00 8'b0
26[15:13]
--
Reserved
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT 16'b0
Remote control Receive register 2 (MII register 27D) 27[15:0] -mg_rem_rd_data RO Remote control read data S0~S15.
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT 16'b0
Remote control Receive register 3 (MII register 28D) 28[15:0] -mg_rem_rd_data RO Vender message M0~M15
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT 16'b0
Remote control Receive register 4 (MII register 29D) 29[15:0] -mg_rem_rd_data RO Vender message M16~M29
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT 16'b0
Remote control Receive register 5 (MII register 30D) 30[15:0] -mg_rem_rd_data RO Vender message M30~M55
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IP113F
Preliminary Data Sheet
Extended MII registers and EEPROM registers (continued) MII ROM NAME R/W DESCRIPTION DEFAULT 0
Switch configuration register 3 (MII register 31D) 31.0 -software_reset R/W Chip software reset SC It is a self-clear bit. All registers are not affected after the software reset is asserted. 1: reset, 0: not reset 31.1 -mg_power_indicate _disable link_list_fail R/W IP113F power abnormal indication disable 1: disable power abnormal notice 0: enable power abnormal notice Link list failure indication bit[2] : TP port link list abnormal bit[3] : Fiber port link list abnormal 1: fail 0: ok BIST Status of embedded SSRAM bit[4] : memory is under testing 1: under testing, 0: testing over bit[5] : memory test result is good when testing over 1: good, 0: fail Auto loopback test enable 1: enable, 0:disable Loopback test T2 timer disable (TS-1000) 1: The MC will not send loopback end indication MF when T2 timer expired 0: The MC will send loopback end MF when T2 timer expired Auto loopback test complete 1: completed, 0: still testing Auto loopback test OK 1: good, 0: fail
0
31[3:2]
--
RO
00
31[5:4]
--
BIST_status
RO
01
31[6] 31[7]
---
mg_auto_loopback _test mg_t2_timer _disable
R/W R/W
0 0
31[8] 31[9] 31[15:10]
----
mg_auto_loopback _complete mg_auto_loopback _ok Reserved
RO RO
0 0
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IP113F
Preliminary Data Sheet
3. Signal Requirements
3.1. Absolute Maximum Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional performance and device reliability are not guaranteed under these conditions. All voltages are specified with respect to GND. Supply Voltage -0.3V to Vcc+0.3V Input Voltage -0.3V to Vcc+0.3V Output Voltage -0.3V to Vcc+0.3V Storage Temperature -55C to 125C Ambient Operating Temperature (Ta) 0C to 70C 3.2. DC Characteristic
Operating Conditions Parameter Supply Voltage Operation Junction Temperature Power Consumption Input Clock Parameter Frequency Frequency Tolerance I/O Electrical Characteristics Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Sym. VIL VIH VOL VOH 2.0 0.4 VCC_I O-0.4 Min. Typ. Max. 0.8 Unit V V V V IOH=4mA IOL=4mA Conditions -100 Sym. Min. Typ. 25 Max. +100 Unit MHz PPM Conditions Sym. VCC Tj Min. 2.375 Typ. 2.5 TBD 0.475 Max. 2.645 Unit V C W Conditions
VCC=2.5v
4. Order Information
Part No. IP113F Package 48-PIN LQFP Notice -
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IP113F
Preliminary Data Sheet
5. Package Detail
48 37
1
36
PH
12
25
13
HE
24
"E"
12" A2 GAUGE PLANE L L1 DETAIL "E" 13 24 Symbol A 12
2
D
E
unit
mm 1.600MAX. 0.050~0.150 1.400 + 0.05
A1 inch 0.0630MAX. 0.0020~0.0059 0.0551 + 0.0020
F SEATING PLANE
0.254
Fy
e
b 12"
D
c
25
A1 A2 b c D E e Hd
-
-
0.200TYP 0.127TYP 7.000 + 0.100 7.000 + 0.100
0.0078TYP 0.0050TYP 0.2756 + 0.0039 0.2756 + 0.0039
2
-
-
1
36
He L L1 y
0.500TYP 9.000 + 0.250 9.000 + 0.250 0.600 + 0.150
-
0.0196TYP 0.3543 + 0.0098 0.3543 + 0.0098
0.0236 + 0.006 0.0393REF 0.0039MAX. 0"~7"
48
37
1.000REF 0.100MAX. 0"~7"
Notes: 1. DIMENSION D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSION. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION / INTRUSION. 3. MAX. END FLASH IS 0.15MM. 4. MAX. DAMBAR PROTRUSION IS 0.13MM. GENERAL APPEARANCE SPEC SHOULD BE BASED ON FINAL VISUAL INSPECTION SPEC.
IC Plus Corp.
Headquarters 10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2, Hsin-Chu City, Taiwan 300, R.O.C. TEL : 886-3-575-0275 FAX : 886-3-575-0475 Website : www.icplus.com.tw
Confidential. Copyright (c) 2003, IC Plus Corp.
Sales Office 4F, No. 106, Hsin-Tai-Wu Road, Sec.1, Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C. TEL : 886-2-2696-1669 FAX : 886-2-2696-2220
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A

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